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Job ID: 147504135
Skills:
Performance Modeling, cycle-accurate simulation, bandwidth latency closure, on-chip interconnects, UCIe, traffic modeling, systemverilog, NoC generators, Rtl Design, cache-coherency protocols, NoC design, coherent fabrics, NoC topologies
Skills:
Ovm, System Verilog, Synthesis Design Compiler, RTL Verilog, Static Timing Analysis PrimeTime, Power analysis tools, Uvm
Skills:
Dsp, Gpu, C, Python, FP8, broadcast networks, PPA optimization, RTL SystemVerilog, output weight row-stationary, deep-learning operators, AI-accelerator micro-architecture, convolution, INT8, Rtl Design, mixed-precision, arithmetic FP32, matrix-multiply dataflows, sparsity acceleration techniques, compute datapath, BF16, AI compiler development, attention, high-throughput arithmetic datapaths, numerical formats, performance utilization models, GEMM, systolic spatial arrays
Skills:
Perl, Verilog, Python, Tcl, Signoff, Formal equivalence, IP integration, Full-chip aspects, Timing convergence, Physical Design, VHDL, Low Power Checks, Timing Verification
Skills:
Pcie, timing-aware micro-architecture, UCIe, high-speed lane alignment, SystemVerilog RTL, CXL, physical-closure collaboration, deskew, design-for-test