Performance Modeling, cycle-accurate simulation, bandwidth latency closure, on-chip interconnects, UCIe, traffic modeling, systemverilog, NoC generators, Rtl Design, cache-coherency protocols, NoC design, coherent fabrics, NoC topologies

Ovm, System Verilog, Synthesis Design Compiler, RTL Verilog, Static Timing Analysis PrimeTime, Power analysis tools, Uvm

Dsp, Gpu, C, Python, FP8, broadcast networks, PPA optimization, RTL SystemVerilog, output weight row-stationary, deep-learning operators, AI-accelerator micro-architecture, convolution, INT8, Rtl Design, mixed-precision, arithmetic FP32, matrix-multiply dataflows, sparsity acceleration techniques, compute datapath, BF16, AI compiler development, attention, high-throughput arithmetic datapaths, numerical formats, performance utilization models, GEMM, systolic spatial arrays

Perl, Verilog, Python, Tcl, Signoff, Formal equivalence, IP integration, Full-chip aspects, Timing convergence, Physical Design, VHDL, Low Power Checks, Timing Verification

Pcie, timing-aware micro-architecture, UCIe, high-speed lane alignment, SystemVerilog RTL, CXL, physical-closure collaboration, deskew, design-for-test

Tcl, Verilog, Python, Perl, IP integration, VHDL, Signoff, Timing Verification, Physical Design, Full-chip aspects

Verilog, Soc Architecture, Digital Design, SoC development, synthesis flows, project planning tools, systemverilog, Timing Closure, integration flows, micro-architecture planning, Rtl Design, industry-standard IPs

Usb, Mac, Perl, Pcie, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Ovm, Test and coverage plan, Assertion checkers, System Verilog HVL, VMM Test Harness, Uvm, Validation plan, Coverage and scenario creation, Verification environment