Design Engineer II

C, Pcie, Ethernet, Python, Calibration compliance lab suites, Verilog RTL coding, ESD Latchup HTOL tests, Analyzers, Oscilloscopes, High speed SERDES, UCIe, Debug skills, Lab automation scripts, Bit Error Rate Testers, CXL, Electrical and Protocol Interoperability and Compliance test suites, Protocol Exercisers, Signal and Power integrity checks, Post-Silicon PHY Systems Interop and Compliance testing

C, Pcie, Ethernet, Python, Calibration compliance lab suites, Verilog RTL coding, ESD Latchup HTOL tests, Analyzers, Oscilloscopes, High speed SERDES, UCIe, Debug skills, Lab automation scripts, Bit Error Rate Testers, CXL, Electrical and Protocol Interoperability and Compliance test suites, Protocol Exercisers, Signal and Power integrity checks, Post-Silicon PHY Systems Interop and Compliance testing

conformal lec , redhawk , Clp, Shell, Verilog, Python, Tcl, Synthesis, Fishtail, pegasus, RTL, Tempus, systemverilog, Innovus, SDC, Joules, VHDL, EDA Tools, Genus

Usb, Tcl, Verilog, Ethernet, Git, Ecos, C, Perforce, Python, Pcie, DDR, static RTL checks, Cadence Mentor simulation suites, Xilinx Vivado, systemverilog, Synthesis, Axi, FPGA design tools, Intel Quartus, low power design techniques, AMBA bus protocols, Rtl Design, Lattice Diamond, STA timing closure, SoC architectures