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The role will be a key player in organization responsible for Characterizing and validating Analog and Digital IP based Silicon Solutions at Cadence.
Candidate should possess strong leadership skills with ability to manage multiple priorities and guide team members on day-to-day lab tests and silicon characterization activities. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication skills, are must have attributes in this role. Coordination with R&D, Marketing teams in defining the scope and delivering the results in time are critical.
EXP: 2-5 yrs or Equivalent or Relavent
Minimum Qualifications & Professional Experience:
. 2-5 years (with BTech) or 4 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
. 2-3 years of management experience leading/mentoring a small team of engineers
. Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/
. Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
Cadence is a health technology company helping the nation’s most patient-centric health systems deliver more consistent, proactive healthcare every day. Cadence’s remote patient intervention solution couples powerful new technology with clinical excellence, providing its patients a precise and personal level of care all outside of the four walls of the hospital.At Cadence, we aim to exceed the expectations of our patients, clinicians, and partners every day. Our team values trust and autonomy, and we empower one another to make decisions, solve problems and build something better. We give clear, candid feedback with the utmost honesty and encouragement. If you’re interested in joining us, explore opportunities at www.cadence.care.
Job ID: 148342201
Skills:
C, Pcie, Ethernet, Python, Calibration compliance lab suites, Verilog RTL coding, ESD Latchup HTOL tests, Analyzers, Oscilloscopes, High speed SERDES, UCIe, Debug skills, Lab automation scripts, Bit Error Rate Testers, CXL, Electrical and Protocol Interoperability and Compliance test suites, Protocol Exercisers, Signal and Power integrity checks, Post-Silicon PHY Systems Interop and Compliance testing
Skills:
conformal lec , redhawk , Clp, Shell, Verilog, Python, Tcl, Synthesis, Fishtail, pegasus, RTL, Tempus, systemverilog, Innovus, SDC, Joules, VHDL, EDA Tools, Genus
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