Design Engineer I
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What we are looking for :
Minimum Qualifications:
. 2-10 years (with Btech) or 8 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
. 2-3 years of management experience leading/mentoring a small team of engineers
. Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on PCIe/CXL/UCIe/Ethernet.
. Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
Preferred Qualifications:
. Experience leading System testing efforts for SERDES solutions.
. Experience in PCIe/UCIe LTSSM states is a plus.
. 1-2 years of experience in FPGA Design and Schematic design.
. 1-2 years of IP/SoC Physical Layer Electrical Validation experience is a plus.
. Familiarity with Verilog RTL coding for FPGA, python,C/C++
. Good communication skills
Cadence is a health technology company helping the nation’s most patient-centric health systems deliver more consistent, proactive healthcare every day. Cadence’s remote patient intervention solution couples powerful new technology with clinical excellence, providing its patients a precise and personal level of care all outside of the four walls of the hospital.At Cadence, we aim to exceed the expectations of our patients, clinicians, and partners every day. Our team values trust and autonomy, and we empower one another to make decisions, solve problems and build something better. We give clear, candid feedback with the utmost honesty and encouragement. If you’re interested in joining us, explore opportunities at www.cadence.care.
Job ID: 150517409
Skills:
redhawk , Python, Perl, Tcl, Sta, Multi-voltage domains, primetime, Foundry PDKs, Tempus, Cadence, Cadence Innovus, Power gating, UPF, Voltus, Implementation tool suite, SDC, Signoff tools, EDA Tools, Physical Design, TSMC, Samsung, CPF, Synopsys, Synopsys ICC2, Low-power design techniques, Timing Analysis
Skills:
Programmable Logic Devices, Safety Requirements, Altium Designer, IGBTs, Microcontrollers, High Current Power Semiconductor Selection, Board-Level Power Supplies, signal conditioning, schematic capture, Diodes, Pcb Layout, Hardware Design, DSPs, Environmental Reliability, Power Converter Circuit Simulation Tools, Gate Drive and Protection Circuit Design
Skills:
manufacturing drawings , Mobile hydraulics applications, Hydraulic Schematic and circuit design, Ratio Projects, Forgings and machining process, NVH Analysis, Design and manufacturing of castings, Weight reduction analysis, Axial Piston pumps, Problem solving methods, ISO-GPS standards, Digital Pump Software-Controlled Pump Design, CAD models
Skills:
System Verilog, Synthesis, microarchitecture specification, Complex Control Logic, Lint closure, Post-Silicon Debug, Timing Constraints, Networking ASICs, Designing Fabric Network On Chip, RTL coding in Verilog, Digital Design
Skills:
Design simulations using pSPICE, Working on processors, Microcontrollers, Electronic Circuit Design, Schematic design using Allegro, Engineering documentation, Dfmea, FPGA development, Component risk assessment
