redhawk , Python, Perl, Tcl, Sta, Multi-voltage domains, primetime, Foundry PDKs, Tempus, Cadence, Cadence Innovus, Power gating, UPF, Voltus, Implementation tool suite, SDC, Signoff tools, EDA Tools, Physical Design, TSMC, Samsung, CPF, Synopsys, Synopsys ICC2, Low-power design techniques, Timing Analysis

Programmable Logic Devices, Safety Requirements, Altium Designer, IGBTs, Microcontrollers, High Current Power Semiconductor Selection, Board-Level Power Supplies, signal conditioning, schematic capture, Diodes, Pcb Layout, Hardware Design, DSPs, Environmental Reliability, Power Converter Circuit Simulation Tools, Gate Drive and Protection Circuit Design

manufacturing drawings , Mobile hydraulics applications, Hydraulic Schematic and circuit design, Ratio Projects, Forgings and machining process, NVH Analysis, Design and manufacturing of castings, Weight reduction analysis, Axial Piston pumps, Problem solving methods, ISO-GPS standards, Digital Pump Software-Controlled Pump Design, CAD models

System Verilog, Synthesis, microarchitecture specification, Complex Control Logic, Lint closure, Post-Silicon Debug, Timing Constraints, Networking ASICs, Designing Fabric Network On Chip, RTL coding in Verilog, Digital Design

Design simulations using pSPICE, Working on processors, Microcontrollers, Electronic Circuit Design, Schematic design using Allegro, Engineering documentation, Dfmea, FPGA development, Component risk assessment

Perl, Verilog, Python, Makefiles, fuse floorsweep design, RTL Build flows, SOC Assembly, Design Automation, Rtl Design, padring, System-On-Chip design implementation flow, SOC integration

Pcie, Perl, Verilog, Python, spyglass, VHDL, DDR memory controllers, CXL

MATLAB, Python, heater drivers, mixed signal IC design, DAC architectures, AMS Designer, biasing circuits, precision references, current sources, Cadence Virtuoso, Spectre