Verilog, Rtl Design, RTL Coding, Micro-architecture, systemverilog, RTL Design Engineer

altium , Orcad, Technical Documentation, Cadence, schematic capture, PCB design principles, hardware development processes, analog and digital circuit design, board bring-up debugging, EMC EMI design concepts, Regulatory Requirements

Usb, DDR, Pcie, Verilog, Ethernet, LINT, cdc, Root Cause Analysis, AMBA protocols, Micro-Architecture Development, systemverilog, Synthesis, Axi, RDC, RTL Coding and Integration, Timing Analysis, APB, SERDES, Design Debug, ASIC SOC design, AHB, Rtl Design

Perl, Shell scripting, Python, Sta, SDC constraints, RTL design using Verilog, ASIC SoC development, Timing Analysis, systemverilog, digital design concepts, VHDL, Functional Verification, RTL debugging, UVM-based verification environments, Timing Closure, synthesis flows

scheduling algorithms , Database Management, multithreading, Numpy, Git, Docker, Python, Cloud Computing, AWS, streamlit, Basilisk, orbital mechanics, stk, multiprocessing, FreeFlyer, GPU acceleration, Orekit, API integrations, gmat

C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation

cadence schematic capture , Hspice, high-speed custom digital design flows, AMs, Cadence Virtuoso, Spectre

FPGA Design, Perl, Verilog, Python, systemverilog, Synthesis Checks, Digital Design, Custom IP Development

astrodynamics , C++, MATLAB, Python, stk, Optimization, Freeflyer, Modeling, Orekit, orbital mechanics, trade studies, gmat, Simulation, Mission design and analysis

C, Clearcase, Cryptography, Aes, Encryption, Clearquest, Perl, Verilog, Python, System Verilog, LINT, cdc, RTL design using Verilog, hash functions, GMAC, signatures, LEC, SHA, private key, ASIC development tools, random number generator