DDR Verification Engineer
DDR Verification Engineer
Randstad Sourceright- Posted 9 hours ago
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Job Description
Position: DDR (BB612FT RM 4439)
Required Skillset
Required Skillset
- Hands-on experience and very good understanding of DDRPHY architecture, DFI protocol and Jedec standards for latest Gens.
- Experience in verification and general computational logic design/verification concepts.
- Working Experience on LPDDR5/LPDDR4 (Must)
- Expertise in Verilog/System Verilog and UVM/OVM.
- Strong debugging, Analytical and problem-solving skills.
- Experience in Scripting languages like Perl would be a plus.
- Post-si bring-up and HW-SW debug experience would be a plus.
- Testplan to Vector Delivery all the assigned task ownership and closure.
- Debug of regression signatures and identifying bug fixes.
- Responsible for Quality sign-off and required documentation.
- Debug and root cause SS/SOC/post silicon issues in collaboration with Design teams.
- Understanding of standard bus protocols like AHB, AXI protocols would be a plus.
- Having the right attitude to learn and quickly adapt to changing industry trends
More Info
Key Skills
AXI protocol
Jedec standards
HW-SW debug
DFI protocol
LPDDR4
Post-si bring-up
DDRPHY architecture
LPDDR5
About Company
Skills:
Ovm, Perl scripting, Verilog, Post-silicon bring-up HW-SW debug, AXI protocol, DDR PHY architecture, Uvm, JEDEC standards, systemverilog, DFI protocol, LPDDR4, debug and root-cause skills, SS SoC post-silicon issues, AHB, LPDDR5