CPU STA Engineer, Sr Lead

General Summary:

Qualcomm Hardware Engineers design, optimize, verify, and test complex electronic systems including circuits, DSPs, FPGAs, and packaging to deliver high-performance, cutting-edge products. In this role, the focus is on electrical integrity and power distribution network (PDN) analysis and optimization, collaborating closely with cross-functional teams to meet stringent power and performance requirements.

Key Responsibilities:

• Perform electrical analyses at block and SoC levels: static/dynamic IR drop, electromigration (EM), power integrity, and ESD verification.
• Drive electrical verification closure at both block and top-level.
• Develop power grid specifications aligned to power, performance, and area (PPA) targets for various SoC blocks.
• Implement power grids using industry-standard place-and-route (PnR) tools.
• Collaborate with Power Integrity (PI) teams to optimize PDN performance.
• Partner with CAD and tool vendors to validate and improve design flows and methodologies.

Minimum Qualifications:

• Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, or related field with 3+ years of hardware engineering experience, OR
• Master's degree with 2+ years, OR
• PhD with 1+ year of relevant experience.
• 4 to 7 years of experience specializing in EM, IR drop, and PDN.

Preferred Qualifications:

• In-depth knowledge and hands-on experience with EM/IR tools such as Synopsys Redhawk and Cadence Voltus.
• Strong background in power grid design and system-level PDN/power integrity concepts.
• Practical knowledge of physical design flows including implementation, verification, power analysis, and static timing analysis (STA).
• Proficiency in scripting languages like TCL, Perl, and Python for automation and flow development.
• Experience working with PnR tools and physical design environments.
• Strong communication and teamwork skills to work with cross-functional teams effectively.