ASIC Silicon Design Engineer

Role Responsibilities:

• Develop and debug RTL designs using Verilog/System Verilog.
• Define microarchitecture details, including interface protocols and data flow.
• Perform RTL quality checks, including Lint, CDC, Synthesis, and UPF checks.
• Collaborate with cross-functional teams to deliver optimized interconnect blocks and ensure adherence to specifications.

Job Requirements:

• Bachelor's degree in Electrical or Computer Engineering, or equivalent practical experience.
• Experience with digital design in ASIC and RTL design using Verilog/System Verilog.
• Experience with scripting languages like Python or Perl.
• Familiarity with ARM-based SoCs, interconnects, and ASIC methodology.