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We are seeking a highly skilled ASIC Physical Design, Sr Staff Engineer to join our team in India. In this role, you will be responsible for the physical design and implementation of high-performance ASICs, collaborating closely with cross-functional teams to ensure successful project delivery.
Job ID: 115963861
Skills:
static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis
Skills:
cdc, RTL Coding, Synthesis, Rtl Design, DV debug, Debug, Dft, ip design
Skills:
rc extraction , routing, Tempus, LVS, Cadence layout tools, Innovus, ERC, STA timing closure, DRC, Placement, Caliber tool, IR EM analysis, block level low power aware floorplanning, tape out activities, Clock Tree Synthesis
Skills:
Synthesis, physical design implementation, RTL to GDS implementation, signoff
Skills:
power integrity , Tcl, Python, Perl, Debugging, Static Timing Verification, Power Integrity Analysis, Automation Scripts, Physical Verification, Timing ECO Implementation, Equivalence Checks, Physical Design, Physical Design Verification, formal verification, Timing Closure, CTS Strategies, Hierarchical Floor Planning
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