static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

cdc, RTL Coding, Synthesis, Rtl Design, DV debug, Debug, Dft, ip design

rc extraction , routing, Tempus, LVS, Cadence layout tools, Innovus, ERC, STA timing closure, DRC, Placement, Caliber tool, IR EM analysis, block level low power aware floorplanning, tape out activities, Clock Tree Synthesis

Synthesis, physical design implementation, RTL to GDS implementation, signoff

power integrity , Tcl, Python, Perl, Debugging, Static Timing Verification, Power Integrity Analysis, Automation Scripts, Physical Verification, Timing ECO Implementation, Equivalence Checks, Physical Design, Physical Design Verification, formal verification, Timing Closure, CTS Strategies, Hierarchical Floor Planning

Synthesis and PnR (Place & Route), Static Timing Analysis (STA), RTL to GDS Flow, Synopsys Fusion Compiler, Tcl/Unix/Perl Scripting, Low Power Design Methodologies

Automation Scripting, floorplanning, ASIC Design, EDA Tools