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Job Description:
Roles & Responsibilities:
To be part of a highly skilled ASIC Team working on the newest technology nodes
Responsible for overall IP/Block and sub-system verification from test plan creation, System Verilog/UVM testbench development to signoff
Ensure first pass product through verification coverage and sign-off criteria
Mentoring and coaching junior team members
Pair with similar domain specialists across other geographical locations on core technical initiatives
Required Skills:
Should have expertise in IP/Block/Subsystem level verification
Proven track record of building test plan, UVM Environment and test benches
Experience with RTL debugging, scoreboard, assertions, functional coverage coding and code coverage analysis
Sound knowledge of Verilog and System Verilog languages
The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.
Educational Qualification:
M.S./M.Tech, BS/BE (Electronics)
Experience Required : 5+ Years in Design Verification (Genuine experience)
Mandatory Skills:
- Should have working knowledge of AXI/AHB protocols.
- Should have worked on complex industry standard or internal protocols. Few examples, DDR, PCIe, NVMe etc.
- Should have working experience on IP/Block/Subsystem Verification starting from verification plan to sign off of the IP.
- Should be expert in System Verilog and UVM methodology.
Additional Skills:
Experience with NVMe is a definite plus
Domain:
- IP/Block/Subsystem Verification (RTL Front end verification)
Location: Bengaluru/ Hyderabad.
Job ID: 145416155