EMIR, Mentor Graphic Caliber, Antenna check, DRC, LVS, Cadence VLE, TSMC 16 12nm 7nm 5nm 3nm and below, Dfm

layout-dependent effects, LVS, PEX, analog mixed-signal IC design flows, device physics, layout methodology automation, deep-submicron advanced-node technologies, CMOS analog layout techniques, ERC, Cadence Virtuoso, DRC, custom analog IC layout, parasitics

layout techniques for analog and mixed-signal circuits, Cadence Virtuoso Layout Editor VLE VXL, Mentor Graphics Calibre DRC LVS

Electro migration, Analog Layout Engineer, Virtuoso schematic, parasitic analysis, virtuoso

CMOS, VLE/VXL, Analog Layout, Cadence, DRC/LVS, Mask Design