Analog layout Engineer
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Exp level: 2 to 5 years
Location: Bangalore
Notice Period: Immediate joiners are preffered.
Responsibilites:
Required Skills:
Please email Resumes to [Confidential Information]
Job ID: 153635263
Skills:
advanced matching and layout techniques, Cadence Virtuoso Custom Compiler, DRC LVS ERC and PEX, FinFET advanced-node layout, lower-node technologies, Analog Mixed-Signal Layout, MOS resistor capacitor current mirror differential pair and analog IP layouts
Skills:
shielding , matching , Dac, Routing, ADC, EMIR verification, PEX, floorplanning, Cadence Virtuoso Layout XL, LVS, Pll, Analog Mixed-Signal Layout Design, SERDES, advanced technology nodes, Placement, ERC, DRC, Op-Amp, LDO, Bandgap, GXL
Skills:
shielding , DC-DC Converters, Common-centroid layout, PEX, BCD Bipolar-CMOS-DMOS technology, LVS, Interdigitated structures, Calibre, Latch-up prevention, Analog layout techniques, Buck Converters, ERC, DRC, ESD-aware layout practices, Cadence Virtuoso, Guard rings, Device matching, Symmetry
Skills:
Signal integrity considerations, Analog Layout Design, Parasitic Extraction, Power distribution techniques, Analog circuit design principles
Skills:
Synopsys IC Validator, Calibre DRC LVS PEX, high-speed analog and mixed-signal layout design, Custom Compiler, LVS, Cadence Pegasus, DRC, Cadence Virtuoso Layout Suite, ERC checks, 7nm FinFET technology
