advanced matching and layout techniques, Cadence Virtuoso Custom Compiler, DRC LVS ERC and PEX, FinFET advanced-node layout, lower-node technologies, Analog Mixed-Signal Layout, MOS resistor capacitor current mirror differential pair and analog IP layouts

shielding , matching , Dac, Routing, ADC, EMIR verification, PEX, floorplanning, Cadence Virtuoso Layout XL, LVS, Pll, Analog Mixed-Signal Layout Design, SERDES, advanced technology nodes, Placement, ERC, DRC, Op-Amp, LDO, Bandgap, GXL

shielding , DC-DC Converters, Common-centroid layout, PEX, BCD Bipolar-CMOS-DMOS technology, LVS, Interdigitated structures, Calibre, Latch-up prevention, Analog layout techniques, Buck Converters, ERC, DRC, ESD-aware layout practices, Cadence Virtuoso, Guard rings, Device matching, Symmetry

Signal integrity considerations, Analog Layout Design, Parasitic Extraction, Power distribution techniques, Analog circuit design principles

Synopsys IC Validator, Calibre DRC LVS PEX, high-speed analog and mixed-signal layout design, Custom Compiler, LVS, Cadence Pegasus, DRC, Cadence Virtuoso Layout Suite, ERC checks, 7nm FinFET technology

analog circuits , Circuit Design, Custom Layout, Mentor, LVS, Physical Verification, EDA Tools, DRC, Synopsys, Cadence Virtuoso, Layout Design, Siemens tools

ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques