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Analog Layout Engineer |5-8 Yrs | Immediate Joiners ,Bangalore
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We are looking for talented Analog Layout Engineers with strong experience in advanced FinFET technologies to join a leading semiconductor project for a global client.
Key Requirements
✅5-8 years of relevant Analog Layout experience
✅ Expertise in FinFET technologies (7nm / 3nm)
✅ Strong understanding of Analog/Mixed Signal Layout concepts
✅ Experience working on advanced node designs and physical implementation
✅ Candidates from non-Intel client projects preferred
Additional Information
Job ID: 152532431
Skills:
advanced matching and layout techniques, DRC LVS ERC and PEX, Cadence Virtuoso Custom Compiler, FinFET advanced-node layout, lower-node technologies, Analog Mixed-Signal Layout, MOS resistor capacitor current mirror differential pair and analog IP layouts
Skills:
Unix Shell Scripting, perl, Static Timing Analysis, Tcl, ASIC digital implementation flows, Tempus, GAA technologies 2nm and below, Voltus, Digital Genus, Innovus, EMIR, EDA Tools, FinFet nodes 7nm and below, Digital Design Flows
Skills:
receivers , power integrity , power amplifiers , altium , Integration, Schematic design, Analog circuitry, SoC based digital baseband boards, Lab validation, Transmitters, Layout, LNAs, Spice, Compliance Testing, Manufacturability, Signal Integrity
Skills:
design optimization, SDC constraints, Timing Closure, MMMC timing analysis, Logic Synthesis, Formal equivalence checking, Post-route timing analysis, CDC-related timing issues, Physical-aware RTL-to-gate synthesis, PPA optimization, ECO implementation
Skills:
Integrated circuits, Design Rule Checks, Analog Layout Design
