advanced matching and layout techniques, DRC LVS ERC and PEX, Cadence Virtuoso Custom Compiler, FinFET advanced-node layout, lower-node technologies, Analog Mixed-Signal Layout, MOS resistor capacitor current mirror differential pair and analog IP layouts

Unix Shell Scripting, perl, Static Timing Analysis, Tcl, ASIC digital implementation flows, Tempus, GAA technologies 2nm and below, Voltus, Digital Genus, Innovus, EMIR, EDA Tools, FinFet nodes 7nm and below, Digital Design Flows

receivers , power integrity , power amplifiers , altium , Integration, Schematic design, Analog circuitry, SoC based digital baseband boards, Lab validation, Transmitters, Layout, LNAs, Spice, Compliance Testing, Manufacturability, Signal Integrity

design optimization, SDC constraints, Timing Closure, MMMC timing analysis, Logic Synthesis, Formal equivalence checking, Post-route timing analysis, CDC-related timing issues, Physical-aware RTL-to-gate synthesis, PPA optimization, ECO implementation

Integrated circuits, Design Rule Checks, Analog Layout Design

Layout Design, Mask layouts for analog digital and mixed-signal ICs, DRC LVS and reliability checks, Mentor Graphics, Synopsys Calibre, Cadence Virtuoso

Perl, Python, Analog power product testing, Pcb Layout, Multimeters, Debug troubleshooting, High current testing, Oscilloscopes, Spectrum Analyzers

Schematic layout tools, Technical reports and communications, Design FMEA creation and revisions, Analog and digital design, Test plans and test reports

Analog Layout, Signal integrity considerations, Parasitic Extraction, Power distribution techniques, Analog circuit design principles