Analog Layout Design Engineer

• Hands-on development of layout for next-generation DDR/HBM/UCIe IPs.
• Creating floorplans, routing, and performing physical verifications to meet quality standards.
• Debugging and solving complex layout issues to ensure high-quality deliverables.
• Collaborating with design engineers to optimize layout for performance, power, and area.
• Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation.
• Ensuring compliance with DRC, LVS, ERC, and antenna rules.

The Impact You Will Have:

• Contribute to the development of cutting-edge technologies that drive the Era of Smart Everything.
• Enhance the performance and reliability of next-generation semiconductor IPs.
• Accelerate the time-to-market for high-performance silicon chips.
• Reduce risks associated with layout design by adhering to stringent verification requirements.
• Foster a collaborative and innovative work environment.
• Support Synopsys mission to lead in chip design and software security.

What You'll Need:

• BTech/MTech in Electrical Engineering or related field.
• 2+ years of relevant experience in analog layout design.
• Proficiency in developing quality layouts and performing physical verifications.
• In-depth understanding of deep submicron effects and floorplan techniques.
• Experience with CMOS, FinFET, and GAA process technologies at 7nm and below.
• Knowledge of layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation.