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Analog Engineer
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Analog Engineer
Quess CorpThis job is no longer accepting applications
Job Description
MNC Hiring: Analog Mixed Signal Layout Engineer
We are looking for an experienced Analog Mixed Signal Layout Engineer for an exciting opportunity with our MNC client.
Location: Hyderabad
Work Mode: Onsite (5 days a week)
Experience: 5+ years of relevant experience
Education: B.E./B.Tech/M.E./M.Tech in Electrical Engineering
Mandatory Skills:
- 5+ years of hands-on experience in independent block/module layout design
- Strong experience with Cadence Layout Design Tools
- Mandatory experience in TSMC 5nm or lower technology nodes
- Experience in custom layouts for high-speed Analog/Digital blocks
- Hands-on experience with Cadence Virtuoso EXL/GXL and Calibre
- Experience in layouts of Ring Oscillators, Dividers, Bias Blocks, Voltage & Current References, and Pre-drivers
- Strong knowledge of layout design, verification, debugging, and sign-off flows
- Experience in module/macro-level layout and layout integration
Good to Have:
- Knowledge of SHELL, PERL, and SKILL scripting
- Experience with Excel
Responsibilities:
- Develop and deliver high-quality custom layout designs.
- Independently debug and resolve layout issues across verification flows.
- Take ownership and accountability for assigned blocks and macros.
- Run release flows and ensure timely closure while adhering to project milestones.
- Coordinate with team members for block-level specifications and top-level integration.
- Complete all required layout verification and sign-off flows.
- Prepare documentation as per project requirements.
Interested candidates can share their updated CV along with relevant details.
#Hiring #AnalogLayout #MixedSignalLayout #VLSIJobs #PhysicalDesign #CadenceVirtuoso #Calibre #TSMC #SemiconductorJobs #HyderabadJobs #VLSI #AnalogDesign
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Key Skills
About Company
Skills:
Verilog, Matlab, analog mixed-signal behavioral model development, AFS, high-resolution low-power ADC architectures, IC design CAD tools, lab instruments, design optimization verification, Spectre, analog CMOS integrated circuit design, IC technology and layout, Spice, transistor-level CMOS analog and mixed-signal blocks, VHDL, mixed-mode simulation tools, Siemens Symphony, Cadence Virtuoso, schematic entry
Skills:
Vcs, shell scripting, Python, Tcl Scripting, Lsf, AI ML, Object Oriented Programming, Linux, Perl, Virtuoso-L, Xcelium, Quantus, Cadence custom IC Virtuoso, parasitic extraction tools, StarRC, Synopsys custom compiler, Primesim, EM IR STA, Finesim, analog circuit simulation flows, Virtuoso-XL, XA, Cadence language, circuit simulation debugging, Spectre, CMOS concepts
Skills:
Vcs, shell scripting, Static Timing Analysis, Python, Tcl Scripting, Ml, Lsf, Object Oriented Programming, Linux, Perl, Virtuoso-L, Xcelium, Cadence custom IC Virtuoso platform, Quantus, parasitic extraction tools, CAD simulation, StarRC, Synopsys custom compiler, Primesim, EM IR STA, Finesim, analog circuit simulation flows, Virtuoso-XL, Ai, XA, Cadence language, circuit simulation debugging, Spectre, CMOS concepts
Skills:
deciphering circuit behavior from schematics, DC analysis, netlist simulation, debugging gate level simulation failures, debug failures and provide fixes at gate or transistor level, latch based designs, timing requirements, circuit simulation with spice simulators, spice correlation, path delay simulations, gate level simulation, transient analysis, timing arcs, circuit characterization timing libraries, Verilog MOS switch level models
Skills:
shielding , matching , Cadence Virtuoso Custom Layout, PEX, 5nm FinFET, Tapeout, Device layout, LVS, Advanced-node design rules, Post-layout analysis, ERC, DRC, Common-centroid, Isolation, Calibre PVS, Guard rings, Parasitic Extraction