Verilog, Matlab, analog mixed-signal behavioral model development, AFS, high-resolution low-power ADC architectures, IC design CAD tools, lab instruments, design optimization verification, Spectre, analog CMOS integrated circuit design, IC technology and layout, Spice, transistor-level CMOS analog and mixed-signal blocks, VHDL, mixed-mode simulation tools, Siemens Symphony, Cadence Virtuoso, schematic entry

Vcs, shell scripting, Python, Tcl Scripting, Lsf, AI ML, Object Oriented Programming, Linux, Perl, Virtuoso-L, Xcelium, Quantus, Cadence custom IC Virtuoso, parasitic extraction tools, StarRC, Synopsys custom compiler, Primesim, EM IR STA, Finesim, analog circuit simulation flows, Virtuoso-XL, XA, Cadence language, circuit simulation debugging, Spectre, CMOS concepts

Vcs, shell scripting, Static Timing Analysis, Python, Tcl Scripting, Ml, Lsf, Object Oriented Programming, Linux, Perl, Virtuoso-L, Xcelium, Cadence custom IC Virtuoso platform, Quantus, parasitic extraction tools, CAD simulation, StarRC, Synopsys custom compiler, Primesim, EM IR STA, Finesim, analog circuit simulation flows, Virtuoso-XL, Ai, XA, Cadence language, circuit simulation debugging, Spectre, CMOS concepts

deciphering circuit behavior from schematics, DC analysis, netlist simulation, debugging gate level simulation failures, debug failures and provide fixes at gate or transistor level, latch based designs, timing requirements, circuit simulation with spice simulators, spice correlation, path delay simulations, gate level simulation, transient analysis, timing arcs, circuit characterization timing libraries, Verilog MOS switch level models

shielding , matching , Cadence Virtuoso Custom Layout, PEX, 5nm FinFET, Tapeout, Device layout, LVS, Advanced-node design rules, Post-layout analysis, ERC, DRC, Common-centroid, Isolation, Calibre PVS, Guard rings, Parasitic Extraction

layout techniques for analog and mixed-signal circuits, Cadence Virtuoso Layout Editor VLE VXL, Mentor Graphics Calibre DRC LVS