Analog Design, Sr Staff Engineer

Debugging, mixed signal CMOS IC design, silicon testing, Analog Design, ADC design

arm architecture , Encryption, Ecc, concurrency, testplan development, Compression, CHI, SOC power management, latency, clock reset, DDR Interconnects, system level aspects, Uvm, Design, Coherency bus interconnects, micro-architecture, interconnect protocols, IP architecture, Ace, bandwidth, Axi, ACE-Lite, AHB, Verilog logic design principles

MATLAB, Transistor Level Design, Verilog A modeling, RF High-Speed broadband techniques, Simulink, Ultra-low-power analog circuits, High-speed data converter architectures, Digitally assisted analog circuits

MATLAB, Transistor Level Design, Ultra-low-power analog circuits, Digitally assisted analog circuits, Simulink, High-speed data converter architectures, RF High-Speed broadband techniques, Verilog A modeling

power converters , post layout parasitic extraction, Monte Carlo analysis, signal chain analysis, bandgaps, BCD process technologies, IC system partitioning, Spectre, Cadence tool set, switching regulators, schematic generation, DACs, VHDL, charge pumps, Amplifiers, architectural tradeoff analysis, Spice, Transistor Level Design, Comparators, IC CAD tools, top-down methodologies, analog and mixed signal design, precision analog control