Debugging, mixed signal CMOS IC design, silicon testing, Analog Design, ADC design

arm architecture , Encryption, Ecc, concurrency, testplan development, Compression, CHI, SOC power management, latency, clock reset, DDR Interconnects, system level aspects, Uvm, Design, Coherency bus interconnects, micro-architecture, interconnect protocols, IP architecture, Ace, bandwidth, Axi, ACE-Lite, AHB, Verilog logic design principles

MATLAB, Transistor Level Design, Verilog A modeling, RF High-Speed broadband techniques, Simulink, Ultra-low-power analog circuits, High-speed data converter architectures, Digitally assisted analog circuits

MATLAB, Transistor Level Design, Ultra-low-power analog circuits, Digitally assisted analog circuits, Simulink, High-speed data converter architectures, RF High-Speed broadband techniques, Verilog A modeling

power converters , post layout parasitic extraction, Monte Carlo analysis, signal chain analysis, bandgaps, BCD process technologies, IC system partitioning, Spectre, Cadence tool set, switching regulators, schematic generation, DACs, VHDL, charge pumps, Amplifiers, architectural tradeoff analysis, Spice, Transistor Level Design, Comparators, IC CAD tools, top-down methodologies, analog and mixed signal design, precision analog control

temperature sensors , System Design, High Voltage charge pumps, Analog IP design, Silicon Characterization, Oscillators, ADCs, Probing, Current and Voltage reference, DC-DC converter, EDA Tools, Switch capacitor circuits, LDO, Voltage regulators

Silicon Validation, Debug, Block designs, Monte Carlo analysis, Design extraction, Simulation and Verification, Design Verification, Analog layouts, Analog Circuit Design, Schematic generation, Simulation flows

CMOS/FinFET Technology (28nm and below), Analog Mixed-Signal Layout, DDR/HBM IP Design, ASIC Physical Design Flow, Floorplanning and DRC/LVS Verification, Layout Automation Scripting