automation, Scripting, SoCs, Real model creation, mixed signal verification fundamentals, PSL SV assertions development, model validation, VerilogA, SV Verilog, environment development, verification planning, Verilog-AMS, verification of Power management IPs, behavioral modelling of analog blocks

System Verilog, Visual Studio Code, Uvm, Spectre, Cadence Xcelium-AMS, Hspice, Mixed-Signal verification, GitHub Copilot

Verilog, Uvm, testbench creation, code coverage analysis, DFI protocols, logic simulation, systemverilog, Verilog-A, score boarding, AMS simulations, RTL debugging

simvision , Aps, Cadence Xcelium, Analog Mixed-Signal AMS SPICE simulation, DMSO, UltraSim, Spectre, Verisium, Fast-SPICE simulators, Spice, Cadence Virtuoso, Xps