Mixed Signal Verification Engg
Job description:
- Development of AMS test plan and checkers or SV assertions.
- Behavioural model development for analog blocks using Verilog/Verilog-A/Verilog-AMS.
- Functional coverage closure.
Requirements:
- 4+ years of experience in Analog & mixed signal verification domain.
- Good understanding of analog circuits and ability to write behavioural models using verilog/verilogA/verilog-AMS.
- Ability to develop AMS test plan, implement TB components, integrate spice netlists, develop checkers, assertions, coverage, and debugging AMS simulations.
- Interact with Analog, RTL & DV teams to bring up system level scenarios in AMS environment.
- Efficient working knowledge on EDA tools/simulators (Cadence - virtuoso schematic editor, Xcelium,APS/XPS OR Synopsys VCS, Customsim OR Siemens -Questa,Eldo).
- Domain knowledge on analog blocks like BGR, comparator, op-amp, current mirror, charge pump, ADC, and regulator.
- Self-motivated to work effectively & should be able to handle work independently.
- B.E/BTech in ECE, EE or M.E/MTech/MS in Microelectronics, VLSI Design, Integrated Circuits and Systems Engineering, System Level Integration & SoC
