transistor-level layout matching, parasitic effects, Cadence Virtuoso Layout Suite, Synopsys Custom Compiler, physical verification closure, LVS, Calibre DRC LVS, Physical Verification, antenna checks, layout debugging, symmetry, FinFET technology nodes, analog mixed-signal IPs, ERC, DRC, Parasitic Extraction, full-custom layout for IO circuits

Physical Verification, Physical Layout Implementation, Samsung Process Technologies, DRC, LVS, Advanced Semiconductor Technology Nodes, Memory Layout Design

PERL, Python, Tcl, AI tools, Skill, multi-patterning, DRC, LVS, Cadence Virtuoso, cell layout optimization

CMOS fundamentals, PEX, post-layout verification, Siemens EDA tools, LVS, semiconductor device physics, Analog Mixed-Signal IC Design, Analog Layout, ERC, DRC, IC design layout methodologies, Cadence Virtuoso

Automation Scripting, AI-assisted workflows, FinFET, LVS, Dfm, Physical Verification, CMOS, bicmos, EMIR, SiGe, ERC, EDA Tools, DRC, RF layouts, Cadence Virtuoso

analog circuits , synopsys tools , floorplanning, matching techniques, physical verification flows, LVS, transistor-level layout, routing optimization, reliability checks, Mentor Siemens Calibre, Layout Design, ERC, DRC, Cadence Virtuoso, Circuit Design

thermal analysis , manufacturing support , Autocad, Pcb Design, Dfm, Dft, Signal Integrity, 3D Modeling, Layout Optimization, Design Rules