power optimization , rtl development , Perl, Verilog, System Verilog, Python, Tcl, LINT, Formal Verification Methodology, Shell-scripting, Synthesis, Timing Closure, HLS, cdc, power analysis, Micro-architecture Development

C, C++, PERL, Python, Dft, Advantest 93000 tester, test pattern development, APTG, test cell integration

python, C, C++, PERL, Dft, Advantest 93000 tester, test pattern development, 93k test methods, APTG, test cell integration

Zephyr, Spi, Uart, Soc, Rtos, I2c, Python, Pcie, Embedded Linux, secure boot development, BootROM, lab instrumentation, protocol analyzers, embedded firmware systems, bare-metal environments, bootloaders, platform firmware development, Oscilloscopes, peripheral drivers

bus protocols - APB, C, Usb, Uart, Bash, Spi, Perl, Pcie, Verilog, I2c, System Verilog, Python, Tcl, verification methodology, i2s, Uvm, DP, Sd, AHB, Axi

Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, BScan, P1687, TetraMax, ATE patterns, JTAG protocols, Gate level simulation, Tessent tool sets, TestMax

Perl, Verilog, Python, Tcl, formal verification with Cadence LEC, Netlist CLP, Spyglass Lint CDC checks, UPF, clock domain crossing designs, Rtl Design, Synthesis, Logical Equivalence checks, low power design methodology

Perl, Python, Tcl, CDC Lint, low power design, digital circuit design principles, RDC, Timing Analysis Concepts, RTL design synthesis, UPF