Verilog, Python, Perl, design simulation and debug tools, digital design fundamentals, micro-architecture development, computer architecture concepts, systemverilog, Rtl Design

Verilog, System Verilog, Python, Perl, Computer Architecture, Logic Design, high performance computing, Physical Design tools, Lint Synthesis, Digital Signal Processing Techniques, HLS

Static timing analysis, Splunk, Unix, AI ML, Linux, Lsf, Python, Bitbucket, Jenkins, Git, DesignSync, EDA Tools, make, GenAI, Convolutional Networks, CI CD process, SW development and debug tools, Design Verification, reinforcement learning, Graph Neural Networks, Dft, Design revision control, Power-aware flows

Spi, Uart, Verilog, I2c, AHB, LINT, AMBA bus protocols, SoC integration, cdc, RTL Coding, MAS development, Quality check flows, ip design, Microarchitecture, APB, Axi, Medium complexity protocol, Sub-system design

ASIC development cycle, ASIC design methodologies, develop solutions, cross-functional teams, Rtl Design, architecture, Verification