Unix, Ilm, Linux, Python, Tcl, QRC models, back-annotation, Multi-Vt, SPEF correlation, Cadence Tempus, Innovus, glitch analysis, Tempus SI, voltage island timing, ETM

C, C++, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools process, UVM testbenches, automating workflows in a distributed compute environment, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, UVM based verification frameworks, TLM

Perl, Python, Tcl, Innovus, Calibre, Assura, ICC2, Cadence, Synopsys, ICV

Verilog, Embedded Controllers, Firmware, analog-digital co-simulation, mixed-signal simulation, digital control logic, digital RTL design, power management, custom-designed IP solutions, Verilog-A, systemverilog

conformal lec , Clp, Tcl, Python, Perl, ASIC synthesis, Digital design fundamentals, UPF, LEC, IEEE 1801, Cadence Genus, Low-power architecture concepts, Low-power verification flows, CPF-based power intent, STA basics

conformal lec , Unix, Clp, Linux, Tcl, Python, Perl, Cadence Genus, UPF, LEC, IEEE 1801, CPF-based power intent, low-power verification flows, ASIC synthesis

Bit Error Rate Tester (BERT), FPGA Design, Usb, Prototyping, C, C++, Labview, Pcie, Verilog, Ethernet, Python, Tcl, DP, SRIO, FPGA coding, DDRIO, Oscilloscopes, Network Analyzer, Pre-Silicon IP SoC Physical Layer Electrical Validation, Post-Silicon Physical Layer Electrical Validation, JESD204, RTL Coding, High speed SERDES protocol, PCB schematic and layout design

clocking , Arm, Trace32, Multimedia, Microprocessors, Computer Architecture, interconnect safety, Synthesis, Security, ARM Debug, Ace, RTL design flow, Verilog RTL coding, RISC-V, APB, Axi, Reset, ATB, BUS Protocols, Chip Assembly, LINT, RTL signoff tools, Serial Interfaces, cdc, ARM CoreSight ETM, IP Integration, Arm Cortex-M A R processor-based SoC debug infrastructure, External Bus Interfaces, RDC, System modes