Verilog, Ethernet, System Verilog, coverage closure techniques, Flex Ethernet, Otn, Uvm, regression management flows, formal verification, assertion-based test, self-checking testbenches, Interlaken

UVM (Universal Verification Methodology), Verilog, C Programming, CPU Subsystems Verification, Design Verification, systemverilog

C, Makefile, Soc Architecture, Windows, Perl, Linux, Verilog, Python, System Verilog, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification

C, Makefile, Soc Architecture, Windows, Linux, Perl, Verilog, System Verilog, Python, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification

Uvm, testbench architecture, regression management, debug methodologies, verification methodology automation, AI-assisted workflows, verification planning, assertions, verification metrics, systemverilog, functional coverage, constrained-random verification

Coverage models, Uvm, CPU Core Verification, Constrained-random tests, systemverilog, Architecture Validation, Testbenches, Checkers, Scoreboards

System Verilog, Unix, Shell, Linux, Python, Constraint based Random verification, Coverage strategies and measurement, Skill, Test cases coding, Uvm, Digital Design and Verification methodologies, VIP coding, Test Plan design

C, Uart, Pwm, Tcl, Verilog, System Verilog, I2c, Python, Perl, AMBA AHB, Uvm, i2s, SDIO, QEI

Verilog, System Verilog, Cadence IES, Synopsys VCS, Uvm, formal property checking tools

Ml, Perl scripting, Python, Tcl, regression management, verification methodologies, AMS Co-Simulation, mixed-signal verification flows, AI-assisted EDA tools, Ai, Uvm, systemverilog, simulation coverage analysis