NOC (Network on Chip), HLS (High-Level Synthesis), power optimization , CDC (Clock Domain Crossing), Cpu, Perl, Verilog, System Verilog, Python, Tcl, LINT, Formal Verification Methodology, Shell-scripting, Memory and Peripheral Subsystems, Data path development, Synthesis, Timing Closure, Implementation Power methodology development, Micro-architecture and RTL development, Power Analysis and Optimization

python, C, C++, PERL, Dft, Advantest 93000 tester, test pattern development, 93k test methods, APTG, test cell integration

Zephyr, Spi, Uart, Soc, Rtos, I2c, Python, Pcie, Embedded Linux, secure boot development, BootROM, lab instrumentation, protocol analyzers, embedded firmware systems, bare-metal environments, bootloaders, platform firmware development, Oscilloscopes, peripheral drivers

Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles

bus protocols - APB, C, Bash, Spi, Pcie, Verilog, I2c, System Verilog, Python, Usb, Uart, Perl, Test Plan Creation, Tcl, gate-level simulations, verification methodology, Uvm, DP, Sd, AHB, Test Development, Gate Level Power-Aware simulations, Axi, i2s, test-bench development, test coverage assessment

static timing analysis, Perl, shell scripting, Python, Tcl, LINT, Synthesis, cdc, SoC integration, UPF-based methodologies, ASIC SOC design, systemverilog, Dft, RTL Verilog, Bluetooth SoCs, low-power design

Shell, Perl, Pcie, Arm, Python, Tcl, MCU, Uvm, UCIe, systemverilog, AMBA, Axi

Perl, Python, Tcl, CDC Lint, low power design, digital circuit design principles, RDC, Timing Analysis Concepts, RTL design synthesis, UPF