Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Tcl, Scripting, Python, Routing, Perl, Fc, Dc, Pt, ICC2, Tempus, LVS, Innovus, Calibre, Synthesis, Physical Verification, formal verification, Placement, EDA Tools, Genus, power analysis, RTL to GDSII, floorplanning, pegasus, LEC, Power Planning, EMIR, ERC, DRC, Physical Design Implementation, ICV

static timing analysis, routing, Innovus, LVS, Parasitic Extraction, Fusion Compiler, DRC, Placement, floorplanning, Clock Tree Synthesis, ICC2

power optimization , Python, Tcl, Physical Verification, Routing Signal Integrity, Low Power Design Techniques, IC Validator ICV, floorplanning, Placement Optimization, Physical Signoff, LVS, Power Planning, Calibre, Physical Design, CTS Clock Architecture, STA Timing Closure, ERC, DRC, ECO Methodologies, MCMM Flows