boundary scan , Jtag, Scripting, Tcl, multi-clock domain designs, DFT signoff, scan architecture, MBIST, DFT architecture, Timing Constraints, ATPG, clocking architectures, silicon bring-up, LBIST, manufacturing test flows, compression methodologies

Design-for-Test (DFT), Static Timing Analysis (STA), C, C++, Verilog, Xml, Low-power design principles, LINT, cdc, Logic Synthesis, 28nm and smaller silicon process technologies, systemverilog, Cadence tool flows, VHDL, Scan testability, formal verification

conformal lec , Clp, Tcl, Python, Perl, Cadence Genus, Synthesis, UPF, LEC, MCMM methodologies, Fusion Compiler, RTL-to-GDS, Low Power Verification, CPF, Formality, Synopsys Design Compiler

static timing analysis, Perl, Tcl, Synthesis, Makefile scripting, physical design CAD flow, Mentor Calibre, Power Distribution, hierarchical P&R, Cadence Innovus, Cadence Genus, Floor Planning, physical design verification

code coverage , closure , automation, Ovm, Tcl Scripting, Verilog, Perl, SDF, GLS, Uvm, RTL, SV, Specman, test-bench development, HVL, assertions development, eRM methodology, formal verification, constraint randomization