Gate Level Simulations, stuck-at transition, Scan Insertion, memory repair solutions, MBIST, JTAG boundary scan, bridge path delay, DFT architecture, EDA Tools, DRC, IEEE 1149.1, ATPG pattern generation, scan chain stitching, DFT rule checks

Python, Perl, Logic Design, Uvm, Post Silicon Testing, SV, DFT Engineering, Architecture Verification, Constrained random testing, Profiling Tools, Coverage metrics

retargeting , boundary scan , DFT architecture, pattern generation validation, MBIST, EDT OCC integration, Boundary Scan JTAG, Scan Architecture, IJTAG, DFT implementation debug, scan implementation, Memory IP Test Simulations

Scan, scripting skills in Perl, tessent DFT, DFT architecture definition, HDLs, Genus, MBIST, Cadence digital implementation tools, Tempus, JTAG boundary scan, ATPG flow implementation

DFT DRC, DFT architecture, Scan Insertion, MBIST Implementation, SoC-level DFT Integration, ATPG, Fault Coverage Analysis, Scan Compression, JTAG IEEE 1149.1, Debug