Calibre, design-rule constraints, FinFET technology nodes, layout optimization, physical verification methodologies, custom layout design, DRC, Parasitic Extraction, LVS, SRAM memory layout, Cadence Virtuoso

Design for Manufacturability (DFM), Design for Yield (DFY), Shell, PERL, Tcl, Physical verification layout methodologies, Skill, DRC, LVS, Memory Layout, Semiconductor design flows

Python, Tcl, QRC, StarRC, Skill, ICC, Cadence Virtuoso, Calibre DRC LVS