NOC (Network on Chip), HLS (High-Level Synthesis), power optimization , CDC (Clock Domain Crossing), Cpu, Perl, Verilog, System Verilog, Python, Tcl, LINT, Formal Verification Methodology, Shell-scripting, Memory and Peripheral Subsystems, Data path development, Synthesis, Timing Closure, Implementation Power methodology development, Micro-architecture and RTL development, Power Analysis and Optimization

Zephyr, Spi, Uart, Soc, Rtos, I2c, Python, Pcie, Embedded Linux, secure boot development, BootROM, lab instrumentation, protocol analyzers, embedded firmware systems, bare-metal environments, bootloaders, platform firmware development, Oscilloscopes, peripheral drivers

Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles

Perl, Bash, Python, Tcl, C, shell scripting, simulation and emulation environments, verification methodologies, Linux Unix environment, SystemVerilog UVM, test plan creation and execution

Tcl, Python, Perl, SVA, Uvm, Functional Coverage, ASIC SoC Subsystem IP verification, systemverilog

Machine Learning, Data Analytics, Deep Learning, Python, LLM-based workflows

UVM (Universal Verification Methodology, SVA (SystemVerilog Assertions, C, Systemc, C++, Shell, Tcl, Arm, Python, Pcie, Perl, systemverilog, UCIe, VC Formal, Verification Methodology, Hardware Emulation Platforms, Formal Model Equivalence Checking Tools, AMBA, MCU, RISC-V, formal verification, Axi