Verilog, C, Python, Perl, Gdb, Indago, SOC design, Cadence

Verilog, Ovm, DFI protocol, JEDEC standards, Uvm, LPDDR5, systemverilog, LPDDR4, DDR PHY verification

arm architecture , C, Firmware, Soc Architecture, Verilog, Embedded Software, Python, Perl, Assembly, CPU architecture, Emulation, systemverilog, AMBA protocols, Simulation

Uart, Nvme, Verilog, I2c, Pcie, Flash, system debug infrastructure, Uvm, system memory hierarchy, AMBA bus protocols, systemverilog, digital ASIC design and verification, formal verification, ARM cores and related infrastructure, CXL, DRAM, CPUSS C-based verification, multi-core SOC, SSP

Ovm, Verilog, System Verilog, C, Systemc, PERL, Shell script, Assembly Language, dpi, SoC Verification, Uvm, Emulation

Debugging RTL Verilog designs, Design Verification