Perl, Shell Scripting, Python, Tcl, Formal Verification Techniques, Mixed-Signal Verification, systemverilog

Perl), scripting languages (TCL, boundary scan , Jtag, Python, Sta, RTL design and verification, SoC design flow, Scan Insertion, MBIST, Fault Models, ATPG, Timing Closure, IEEE 1149.1, LBIST, Compression

New product introduction (NPI), Siemens Mentor Xpedition XPD, IC package layout tools, Substrate manufacturing constraints, Assembly constraints, Power plane design, Basic scripting for automation, Library maintenance, Foundry design rules, Substrate design rules, IC packaging technologies, Cadence APD

Usb, Tcl, Verilog, Arm, System Verilog, Ethernet, Perl, Spi, I2c, Python, Soc Architecture, ASIC design flow, Synthesis, LINT, peripheral IPs, Low-power design, Timing Analysis, Axi, BUS Protocols, MBIST, MIPS, Bus Matrix design, AMBA, Rtl Design, Timing constraint SDC, DFT concepts, Power estimations, RDC, Formal CDC

C, shell scripting, Visual Basic, UNIX, Java, Python, Perl, Linux, Teradyne UltraFLEX platforms, ATE test development, DFT methodologies

caliber , power optimization , partitioning, LEC, Antenna, LVS, ICC, Timing Analysis, primetime, equivalence checks, Physical Verification, Placement, Innovus, Encounter, Sta, floor-planning, formal verification, Crosstalk delay analysis, ERC, DRC, noise analysis, ECO implementation, Clock Tree Synthesis, timing and functional ECOs