Ovm, Perl scripting, Verilog, Post-silicon bring-up HW-SW debug, AXI protocol, DDR PHY architecture, Uvm, JEDEC standards, systemverilog, DFI protocol, LPDDR4, debug and root-cause skills, SS SoC post-silicon issues, AHB, LPDDR5

Verilog, Python, Perl, Gdb, SOC design, Indago, Cadence

Xpath, C++, Gcc, Xslt, Sql, Git, Linux, Xml, Javascript, System Verilog, Python, Assembly languages, SGE or other DRMS, Uvm, HTML DOM, LLVM, SVA

Debugging, C, Shell, Tcl, Verilog, System Verilog, Python, Perl, UVM methodology, constrained random methodologies, Metric Driven Verification, assertions, functional coverage, formal verification methodologies