rtl development , Prototyping, Gdb, Perl, Verilog, Python, ASIC design flow, VCS or equivalent simulation tools, Logic Synthesis, Bring-up, Debug tools like Debussy, Lab debug, Design Verification, Eco, Micro-architecture, Floor-planning, Timing Analysis

VA VE implementation, Tolerance stack up analysis, Proof of Concepts prototyping and testing, CAD software, Dfmea, Plastic Design, Fluid mechanical concepts, Dfm, Design Calculations, SolidWorks PDM, New Product Development, DFA

static timing analysis, Verilog, Python, Tcl, SDC development, Tempus, Cadence Innovus, simulation methodologies, Rtl Design, transistor-level concepts, Genus, digital circuit operation, custom layout fundamentals, place-and-route, multi-clock designs, Synthesis, digital design fundamentals, floorplanning, Physical Verification, systemverilog, CDC concepts, Timing Constraints, Liberty timing models, characterization concepts

micro architecture , X86, Computer Architecture, Arm, Processor Asic design flow, ECO bring up, Design Verification, Fetch Decode Load-Store, high performance microprocessor architecture, L1 L2 caches, Coherency, CPU microarchitecture, Memory Design, Processor Instruction set architecture, PD synthesis, Rtl Design, Prefetch, Memory Ordering Rules, PPA optimization, Power

Design Verification, Debugging RTL Verilog designs

layout verification , very large scale integration (VLSI) design, system on a chip (SoC), System Verilog, clock voltage domain crossing design for testing DFT, ASIC Design, design rules, low power designs

C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation