Memory Architecture, Floor Planning, ERC, Mentor Graphics Calibre, RC requirements, DRC, Antenna, Electro Migration, LVS, ICV, Cadence Virtuoso

Debugging, Physical Verification Tools, PEX, FinFET, LVS, Layout Optimization, ERC, DRC, Post-layout Verification, Analog Custom Layout, High-performance Analog Mixed-Signal Blocks, Advanced Technology Nodes, Cadence Virtuoso

caliber , Verification Tools, Layout Design, Cadence Virtuoso

Network Protocols, Rtos, Wireshark, Agile Methodology, JIRA, Bugzilla, Scripting Languages, Linux, Version Control Systems, Squish, Robot Framework, Debuggers, Selenium, Cucumber, Python, Analyzers, Oscilloscopes, Electronics, IDES, Defect management tools, Software Verification and Validation methodologies, Communication Protocols, Automated testing frameworks

Switch, Pcie, Virtualization, Verification tools for simulation and debug, UFS, XUSB, High Speed IO verification, 1G Ethernet MAC, Uvm, Security, Sensor processing, Memory controller verification, Axi, Interconnect verification, APB, VMM, Safety, CPU verification, formal verification

Synopsys IC Validator, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, Cadence Pegasus, high-speed analog and mixed-signal layout design, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, DRC, parasitic optimization, reliability rules

PERL, Python, Tcl, Skill, AI tools, PPA, multi-patterning, DRC, LVS, cell layout optimization, Cadence Virtuoso