Perl, Python, Tcl, asynchronous logic, state machines, digital design fundamentals, synchronous logic, systemverilog

Verilog, MIPI, FPD-Link, synthesis tools, DFT methodologies, Ethernet MAC PHY, systemverilog, SerDes digital architectures, high-speed digital design

python, perl, static timing analysis, Bash, Tcl, verification flow, digital design fundamentals, Uvm, systemverilog, scripting automation, Rtl Design, VHDL, synthesis tools

Verilog, Debugging Tools, systemverilog, Rtl Design, Synthesis, FPGA Prototyping, Timing Closure, Verification Methodologies, low power design, Physical Design

C, Clearcase, Cryptography, Aes, Encryption, Clearquest, Perl, Verilog, Python, System Verilog, LINT, cdc, RTL design using Verilog, hash functions, GMAC, signatures, LEC, SHA, private key, ASIC development tools, random number generator

FPGA Design, Perl, Verilog, Python, systemverilog, Synthesis Checks, Digital Design, Custom IP Development

Perl, Shell scripting, Python, Sta, SDC constraints, RTL design using Verilog, ASIC SoC development, Timing Analysis, systemverilog, digital design concepts, VHDL, Functional Verification, RTL debugging, UVM-based verification environments, Timing Closure, synthesis flows

Jtag, C, Verilog, System Verilog, Uvm, SOC RTL Design Verification

Clp, Pcie, Qc Tools, IPXACT, cdc, Vlsi, LINT, FIFO, UPF, AMBA, arbitration techniques, SDC, RDC, RTL Coding, VCLP