Modeling, automation techniques, reusable intellectual property, circuit design verification, silicon correlation, analog and mixed-signal IC design, semiconductor device physics, CMOS technologies, AI-driven engineering tools, product qualification, DRAM, advanced process nodes

bandwidth management , Microprocessor Cores, SystemVerilog Assertions, Specman E, Verification and debug of IP subsystem SoCs, Industry-standard simulators, Revision control systems, Constrained-random verification environments, systemverilog, Packet processing, Regression systems, Congestion control, Hierarchical memory subsystems, Full verification life cycle, Vector processing units

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Usb, Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Tcl, Xcelium, Design Verification, QuestaSim, Uvm, systemverilog, Riviera, Axi, MIPI, APB, CXL, AHB, SoC Verification

C, C++, Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, Post-silicon debugging, RTL design and verification flows, Simulation Tools, JTAG protocols, Digital Design, Assembly language programming

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Perl, System Verilog, Tcl, Code functional coverage, Ethernet MAC PCS and SerDes SoC verification, Checkers, Cadence, Uvm, Constrained random verification, BFMs, Block system level verification plans and tests, Gate-level SDF simulations, Scoreboards, Monitors, Ethernet Subsystem SoC verification, Synopsys