Subsystem/SoC Level Verification Engineer

Job Description:

He/she should have strong knowledge of the following with 12-15 years of experience in Ethernet Subsystem/SoC Level Functional verification

• Working experience in Ethernet Subsystem/SoC verification
• Expertise to develop verification environments using System Verilog and UVM
• Expertise to develop BFMs / Checkers / monitors / Scoreboards
• Must have developed block/system level verification plans and tests.
• Must have capability to debug test failures to find the root cause.
• Must have worked on code / functional coverage.
• Experience in constrained random verification.
• Domain skills: Ethernet (MAC, PCS and SerDes)/SoC verification
• Gate-level /SDF simulations
• Knowledge of scripting languages like Perl, Tcl
• Flexible to work in any IP/Subsystem/SoC projects
  
  

CAD Tools: Cadence/Synopsys

Education Qualification: Bachelors/Master's in Electronics/Computer Engg

R026376