automation, Ovm, Tcl Scripting, Verilog, Perl, RTL, GLS, Uvm, SV, Specman, SDF sim debug, test-bench development, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification

GAA (Gate-All-Around, PDK enablement, Planar MOSFETs, Spice model understanding, Foundry PDK enablement, Semiconductor technology analysis, CMOS device physics, Design Automation, Parasitic Extraction, Physical verification decks, Process design interaction, Electrical studies, Cadence-based tool suites, Automation methodology, Co-optimization of PDK components, FinFETs

redhawk , Shell, Tcl, Verilog, PERL, Innovus, floorplan exploration and optimization, Starrcxt, place and route methodologies, physical implementation and analysis tools, Fusion Compiler, power integrity and reliability analysis, Calibre, VHDL, low power physical design flows and methodologies, timing and signal integrity analysis, metal-only ECO implementation, power grid planning and implementation, timing optimization and timing closure, placement and optimization, Clock Tree Synthesis