Sed, Jtag, Awk, Tcl, debug skills, MBIST, gate-level simulation, Spyglass-DFT, test cost reduction analysis, Dft, ATPG, scan-stitching, Scan, scripting skills, LBIST, Tessent flow, post silicon support

scan patterns generation, SSN OCC TAP verification, multi die DFT, Post silicon debug, ICL simulations, ATPG, scan-stitching, Tessent ATPG, timing and no-timing simulations, Pattern retargeting

System Verilog, industry standard EDA tools, fault coverage analysis, Dft, hierarchical scan insertion, ATPG pattern generation, hierarchical MBIST insertion, scan compression methodologies, IJTAG methodology

boundary scan , Jtag, physical design constraints, Sta, Synthesis, verification flows, MBIST, SSN, Rtl Design, ICL, DFT architecture, OCC Integration, Scan Insertion, ATPG, pdl, Scan ATPG, LBIST, IJTAG

Jtag, DFT Engineer, DFT Manager, iJTAG, BSCAN, ATPG, technical ownership, DFT tools

boundary scan , logic bist , Test Automation, DFT Methodologies, Scan Design, Fault Simulation, ATE Programming, Design Debugging, DFT Architecture, Timing Analysis