clocking , Ras, Python Scripting, Gpio, System Verilog, Verification debug tools, Fuse, Uvm, power management, Xeon Global flows, Reset flows, Security flows, Pre silicon validation

lauterbach , Spi, C, Systemc, Usb, Shell, Tcl, Verilog, Jtag, Python, Pcie, Perl, DDR, Axi, Coresight, LPDDR, RTL, UltraSoC, Cadence Palladium, systemverilog, VHDL, Cadence Palladium XP, ZeBu

Linux, Verilog, Unix Scripting, Cadence Palladium, Siemens Veloce, RTL Compilation, Synopsys ZeBu, Debugging Issue Analysis, Pre-Silicon Validation, systemverilog, Emulation Model Build Compilation

C, C++, Shell scripting, Python, Emulation platforms and tools, Hardware emulators, Reproduction of Si issues on palladium, FPGA-based prototyping, EDA tools and associated workflows, Post Silicon debug, Writing C test cases, Running porting SW tests on palladium, Cadence Palladium flows

Perl, Verilog, Python, Tcl, Cadence Palladium, RTL, Digital Design, emulation compile mapping, systemverilog, acceleration, ASIC SoC emulation, UVM-based verification environments, Synopsys ZeBu, runtime concepts, partitioning