Senior Analog Layout Engineer

Location: Bengaluru

Experience: 5–10 Years

Role Overview

We are looking for a Senior Analog Layout Engineer with strong hands-on experience in custom/analog layout at advanced technology nodes, including FinFET.

Key Responsibilities

Develop high-quality analog/custom layouts for complex IC designs.
Work on advanced-node layouts across FinFET technologies such as 5nm, 7nm, 3nm and below.
Execute floorplanning, placement, routing and layout optimization for analog/mixed-signal blocks.
Strong understanding of matching, symmetry, common-centroid, interdigitation and shielding techniques.
Optimize layouts for area, parasitics, performance, matching and reliability.
Perform DRC, LVS, ERC and PEX and resolve physical verification issues.
Work closely with Analog Design, Circuit Design, P&R and Verification teams.
Analyze and minimize parasitic effects and coupling in advanced-node designs.
Support post-layout simulation, design iterations and tape-out activities.

Required Skills

5–10 years of Analog/Custom Layout experience.
Strong experience in advanced technology nodes and FinFET.
Hands-on experience with Cadence Virtuoso and physical verification tools.
Strong understanding of analog layout fundamentals and advanced matching techniques.
Experience with DRC, LVS, ERC, PEX and post-layout verification.
Exposure to low-voltage, high-speed and high-performance analog/mixed-signal blocks.
Experience with 5nm/7nm/3nm or similar advanced nodes is highly preferred.
Strong debugging and layout optimization skills.