Vcs, Perl, Python, Tcl, Xcelium, AMBA-based interconnect fabrics, AXI-Lite, Uvm, systemverilog, Axi, APB, AI-assisted engineering tools, Questa, AHB

boundary scan , ATPG (Automatic Test Pattern Generation), LBIST (Logic Built-In Self-Test), DFT DRC (Design Rule Checking), Jtag, Perl, Python, Tcl, LINT, ASIC design flow, cdc, Scan compression, Scan stitching, Low power DFT Techniques, RTL Coding, ATPG Coverage improvement, DFT STA Constraint development, Analog Phy DFT

Tcl, System Verilog, Python, Perl, Vcs, Questa, Uvm, Modelsim

Oracle Weblogic, Oracle Goldengate, Python, Azure, Groovy

Cadence - Virtuoso, Perl, Python, Tcl, Mentor tools, SV, Verilog Hdl, Cadence, Uvm, Spice Simulator, Verilog-AMS, AMS simulation environment, Verilog-D, Synopsys, Verilog-A

Perl, Pcie, Python, Tcl, SV, ONFI, MBIST, AI tools and Methodologies, Uvm, NAND, DFT architecture, LPDDR, Test controller architecture