Staff Engineer
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
Looking for an experienced senior verification engineer with 8-10 years of experience in ASIC/SOC/IP/block level functional verification using system verilog/UVM.
The ideal candidate will have strong command of UVM, advanced UVM and system verilog
Key responsibilities:
The ideal candidate will have strong command of UVM, advanced UVM and system verilog
Key responsibilities:
- Develop a comprehensive test plan, complete test-bench and robust verification environment including interface agents and scoreboard in UVM.
- Possess deep knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB.
- Strong debugging skills to address TB issues quickly and test failures.
- Take responsibility for verification closure by addressing coverage and managing bug reports.
- Proficiency in using industry standard verification tools such as Questa, VCS or ModelSim.
- Experience with scripting languages like python, perl or TCL for automation tasks.
- Able to track & manage Daily and weekly progress and manage a team of 6 to 7 Engineers.
- Interact with the customer on the tasks and status updates.
More Info
About Company
Skills:
Machine Learning, Data Analytics, Python, Deep Learning, Document-processing pipelines, LLM-based workflows
Skills:
Vcs, Perl, Python, Tcl, Xcelium, AMBA-based interconnect fabrics, AXI-Lite, Uvm, systemverilog, Axi, APB, AI-assisted engineering tools, Questa, AHB
Skills:
boundary scan , ATPG (Automatic Test Pattern Generation), LBIST (Logic Built-In Self-Test), DFT DRC (Design Rule Checking), Jtag, Perl, Python, Tcl, LINT, ASIC design flow, cdc, Scan compression, Scan stitching, Low power DFT Techniques, RTL Coding, ATPG Coverage improvement, DFT STA Constraint development, Analog Phy DFT
Skills:
PowerShell, Python, SOTI MobiControl, HP Thin Clients, Enterprise MDM
Skills:
code coverage , SoC Verification, MCU Verification, Uvm, Functional Coverage, Assertion Coverage