Verilog, Rtl Design, Logic analyzers, systemverilog, DDR memory controller calibration, Calibration algorithms

Digital Logic Design, Rtl Design, SOC Integration, RTL quality checks, Constraints for Subsystem IP, ip design, Processor peripherals

Verilog, systemverilog, DDR memory controller calibration, Rtl Design, Logic analyzers, Calibration algorithms

conformal lec , Perl, Verilog, Python, Tcl, VC spyglass, IPXACT, LINT, Formality, VSI, UPF, 0in, RTL Coding, IORING, SoC IP level integration, Design Partitioning

Unix, Python, Shell, Linux, Skill, SoC Integration, Rtl Design

Python Scripting, PrimeTime or equivalent tools, ASIC design flow, Circuit timing STA, C embedded experience, Digital Design, Low power digital design and analysis, RTL design in Verilog SystemVerilog, ASIC design in sub-20nm technology nodes

Perl, Verilog, Python, SoC Verification, Makefiles, fuse floorsweep design, RTL Build flows, Padring, Design Automation, Rtl Design, Physical Design, Synthesis, Dft, System-On-Chip design implementation flow, SOC integration, Chip Design

Sta, LINT, Memory operation, Synchronous design concepts, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, spyglass, Synthesis, device physics, CDC methodologies